Siplont

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Career

Let’s build something amazing together!

At Siplont, we know that people are the greatest asset of any company. That is why we do not just hire employees – we hire innovators, problem solvers and visionaries who are willing to contribute to change. Whether you are a professional or a graduate eager to kickstart your career, Siplont provides a collaborative work environment for everyone to grow.

We believe in the development of our people and are committed to nurturing talent through continuous learning and career development opportunities. We offer mentorship, learning, and state-of-the-art tools to excel.

Since our inception, we have always focused on creating a culture of openness, creativity, and teamwork – where every idea and every voice is welcome.

Join us at Siplont, and be a part of a forward-thinking team that challenges conventions, embraces bold ideas, and creates real-world solutions.

Check out our current job openings and become a part of a team that’s defining the future.

Design Verification Engineers

Full time

Bangalore, India

DFT Engineers

Full time

Bangalore, India

Physical Design Engineers

Full time

Bangalore, India

RTL Design Engineers

Full time

Bangalore, India

Analog Mixed Signal Layout

Full time

Bangalore, India

Let’s Build the Future Together

Connect with our experts to explore tailored technology solutions for your industry.

Design Verification Engineers

Job Description

  • SOC Verification engineers with 3+ years of experience
  • Knowledge of ARM architecture, CPU fundamentals & Cache coherency
  • Experience with C/C++, assembly, and scripting languages.
  • Familiarity with low-power design and verification
  • Develop CDV UVM verification environments at system level
  • Verify CPU connectivity to IP blocks
  • Develop SoC test plans and test cases and track metrics including code and functional covera

Job Requirement:

  • Bachelor’s or Master’s in EE/CS or related field
  • 3+ years of SoC in ASIC/FPGA verification experience
  • Proficiency in SV and UVM
  • Experience with simulation, emulation, and formal verification
  • Strong debugging and problem-solving skills

Experience (years) :

  • 3+ Years

Education Qualification:

  • BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

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DFT Engineers

Job Description

  • Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IJTAG. and MBIST/LBIST.
  • Experience in Tessent based ATPG flow, GLS and Post-silicon-debug.
  • Hands-on in Perl/Tcl/Python scripting.
  • Excellent analytical, and problem-solving skills.
  • Perform Core and SOC level ATPG to meet Automotive grade quality.
  • Hierarchical ATPG retargeting and Pattern release for application on ATE.
  • Perform SOC and Core level Timing/Non-timing GLS.
  • Silicon bring-up, diagnosis and support for physical failure analysis.
  • Enable Emulation of Gate level SCAN patterns.

Experience (years) :

  • 3+ Years

Education Qualification:

  • BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

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Physical Design Engineers

Job Description

  • We are looking for bright Physical Design Engineer with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering High performance design, flows for high performance SoCs in sub-10nm process for mobile space.

Job Requirement:

  • 2-5 years hands-on experience of different PnR steps including Floor planning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure.
  • Well versed with high frequency design & advanced tech node implementation
  • In depth understanding of PG-Grid optimization, including identification of high vs low current density paths & layer/via optimization, Adaptive PDN experience.
  • In depth knowledge of custom clock tree including H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation.
  • Well versed with tackling high placement density/congestion bottlenecks.
  • In depth knowledge of PnR tool knobs/recipes for PPA optimization.
  • Experience in automation using Perl/Python and tcl.
  • Good communication skills and ability & desire to work in a cross-site cross-functional team environment.

Experience (years) :

  • 3+ Years

Education Qualification:

  • BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

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RTL Design Engineers

Job Requirement:

  • Strong design fundamentals with hands-on experience in front-end design flows
  • Hands-on experience in design of micro-architecture blocks, RTL coding, block-level verification.
  • Hands-on experience in Linting, CDC – analysis of reports, identify ways to fix the violations
  • Hands-on experience in SoC/IP integration
  • Excellent understanding of SoC components like processors, memories, peripherals, IOs
  • Good understanding of at-least one of the protocols like UFS/PCIe/SAS/SATA/USB
  • Experience of working with ARM or ARC (Synopsys) processors/sub-systems
  • Experience of UPF flow, updating constraints
  • Ability to work independently, ramp-up quickly and work with verification/validation teams for front-end flows
  • Good experience in PERL/TCL scripting
  • Good verbal and written communication skills are required.

Experience (years) :

  • 3 – 12 Years

Education Qualification:

  • BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field

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Analog Mixed Signal Layout

Job Requirement:

  • Independent layout development of High Speed blocks like SerDes, Rx, Tx, , PLL, ADC, LDO, Bandgap etc
  • Strong debug skills and good communication

Experience (years) :

  • 3 – 7 Years

Education Qualification:

  • BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.

Apply for this job